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? semiconductor components industries, llc, 2002 may, 2002 rev. 3 1 publication order number: mc33078/d mc33078, mc33079 low noise dual/quad operational amplifiers the mc33078/9 series is a family of high quality monolithic amplifiers employing bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. this family incorporates the use of high frequency pnp input transistors to produce amplifiers exhibiting low input voltage noise with high gain bandwidth product and slew rate. the all npn output stage exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source and sink ac frequency performance. the mc33078/9 family offers both dual and quad amplifier versions and is available in the plastic dip and soic packages (p and d suffixes). ? dual supply operation: 5.0 v to 18 v ? low voltage noise: 4.5 nv/ hz ? low input offset voltage: 0.15 mv ? low t.c. of input offset voltage: 2.0 v/ c ? low total harmonic distortion: 0.002% ? high gain bandwidth product: 16 mhz ? high slew rate: 7.0 v/ s ? high open loop ac gain: 800 @ 20 khz ? excellent frequency stability ? large output voltage swing: +14.1 v/ 14.6 v ? esd diodes provided on the inputs figure 1. representative schematic diagram (each amplifier) v cc d1 q4 q9 q3 q5 pos d3 c2 r7 q11 neg r2 q8 d4 c3 r9 q10 q2 d2 q6 r4 q7 r5 r6 q12 r3 c1 r1 q1 z1 j1 amplifier biasing v ee q3 v out pdip8 p suffix case 626 1 8 so8 d suffix case 751 1 8 marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week dual quad pdip14 p suffix case 646 1 14 so14 d suffix case 751a 1 14 device package shipping ordering information mc33078d so8 98 units/rail mc33078p pdip8 mc33079d so14 50 units/rail 55 units/rail mc33079dr2 so14 2500 tape & reel mc33078dr2 so8 2500 tape & reel mc33079p pdip14 25 units/rail 1 8 mc33078p awl yyww alyw 33078 1 8 1 14 mc33079p awlyyww 1 14 mc33079d awlyww http://onsemi.com
mc33078, mc33079 http://onsemi.com 2 pin connections case 626/751 dual (dual, top view) 4 v ee 1 2 3 5 6 7 8 v cc output 2 inputs 2 inputs 1 - + 1 - + 2 output 1 case 646/751a quad (quad, top view) 1 2 3 4 5 6 7 14 8 9 10 11 12 13 output 1 v cc output 4 inputs 4 output 2 v ee inputs 3 output 3 1 4 23 inputs 1 inputs 2 maximum ratings rating symbol value unit supply voltage (v cc to v ee) v s +36 v input differential voltage range v idr note 1 v input voltage range v ir note 1 v output short circuit duration (note 2) t sc indefinite sec maximum junction temperature t j +150 c storage temperature t stg 60 to +150 c maximum power dissipation p d note 2 mw operating temperature range t a 40 to +85 c 1. either or both input voltages must not exceed the magnitude of v cc or v ee . 2. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded (see figure 2).
mc33078, mc33079 http://onsemi.com 3 dc electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit input offset voltage (r s = 10 , v cm = 0 v, v o = 0 v) (mc33078) t a = +25 c t a = 40 to +85 c (mc33079) t a = +25 c t a = 40 to +85 c |v io | 0.15 0.15 2.0 3.0 2.5 3.5 mv average temperature coefficient of input offset voltage r s = 10 , v cm = 0 v, v o = 0 v, t a = t low to t high d v io / d t 2.0 m v/ c input bias current (v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c i ib 300 750 800 na input offset current (v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c i io 25 150 175 na common mode input voltage range ( v io = 5.0 mv, v o = 0 v) v icr 13 14 v large signal voltage gain (v o = 10 v, r l = 2.0 k ) t a = +25 c t a = 40 to +85 c a vol 90 85 110 db output voltage swing (v id = 1.0v) r l = 600 r l = 600 r l = 2.0 k r l = 2.0 k r l = 10 k r l = 10 k v o + v o v o + v o v o + v o +13.2 +13.5 +10.7 11.9 +13.8 13.7 +14.1 14.6 13.2 14 v common mode rejection (v in = 13v) cmr 80 100 db power supply rejection (note 3) v cc /v ee = +15 v/ 15 v to +5.0 v/ 5.0 v psr 80 105 db output short circuit current (v id = 1.0 v, output to ground) source sink i sc +15 20 +29 37 ma power supply current (v o = 0 v, all amplifiers) (mc33078) t a = +25 c (mc33078) t a = 40 to +85 c (mc33079) t a = +25 c (mc33079) t a = 40 to +85 c i d 4.1 8.4 5.0 5.5 10 11 ma 3. measured with v cc and v ee differentially varied simultaneously.
mc33078, mc33079 http://onsemi.com 4 ac electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit slew rate (v in = 10 v to +10 v, r l = 2.0 k , c l = 100 pf a v = +1.0) sr 5.0 7.0 v/ s gain bandwidth product (f = 100 khz) gbw 10 16 mhz unity gain bandwidth (open loop) bw 9.0 mhz gain margin (r l = 2.0 k ) c l = 0 pf c l = 100 pf a m 11 6.0 db phase margin (r l = 2.0 k ) c l = 0 pf c l = 100 pf m 55 40 deg channel separation (f = 20 hz to 20 khz) cs 120 db power bandwidth (v o = 27 v pp , r l = 2.0 k , thd 1.0%) bw p 120 khz total harmonic distortion (r l = 2.0 k , f = 20 hz to 20 khz, v o = 3.0 v rms , a v = +1.0) thd 0.002 % open loop output impedance (v o = 0 v, f = 9.0 mhz) |z o | 37 differential input resistance (v cm = 0 v) r in 175 k differential input capacitance (v cm = 0 v) c in 12 pf equivalent input noise voltage (r s = 100 , f = 1.0 khz) e n 4.5 nv/ hz equivalent input noise current (f = 1.0 khz) i n 0.5 pa/ hz v cm = 0 v t a = 25 c figure 2. maximum power dissipation versus temperature figure 3. input bias current versus supply voltage figure 4. input bias current versus temperature figure 5. input offset voltage versus temperature p, maximum power dissipation (mw) d -20 0 20 40 60 80 100 120 140 160 t a , ambient temperature ( c) -55 -40 mc33078p & mc33079p mc33079d mc33078d 5.0 10 15 20 v cc , | v ee |, supply voltage (v) i, input bias current (na) ib t a , ambient temperature ( c) 0 25 50 75 100 125 -55 -25 v cc = +15 v v ee = -15 v v cm = 0 v v, input offset voltage (mv) io t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 unit 1 unit 2 unit 3 v cc = +15 v v ee = -15 v r s = 10 w v cm = 0 v a v = +1 i, input bias current (na) ib 2400 2000 1600 1200 800 400 0 800 600 400 200 0 1000 800 600 400 200 0 2.0 1.0 0 -1.0 -2.0
mc33078, mc33079 http://onsemi.com 5 sink source v cc = +15 v v ee = -15 v r l < 100 w v id = 1.0 v -55 c 25 c v cc = +15 v v ee = -15 v 125 c -55 c 125 c 25 c figure 6. input bias current versus common mode voltage figure 7. input common mode voltage range versus temperature figure 8. output saturation voltage versus load resistance to ground figure 9. output short circuit current versus temperature figure 10. supply current versus temperature figure 11. common mode rejection versus frequency i, input bias current (na) ib -15 -10 -5.0 0 5.0 10 15 v cm , common mode voltage (v) v cc = +15 v v ee = -15 v t a = 25 c v icr voltage range -v cm -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) +v cm v cc = +3.0 v to +15 v v ee = -3.0 v to -15 v d v io = 5.0 mv v o = 0 v | i|, output short circuit current (ma) sc t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 i, supply current (ma) cc t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 10 v 15 v 15 v 10 v 5.0 v 5.0 v v cm = 0 v r l = v o = 0 v mc33078 mc33079 supply voltages cmr, common mode rejection (db) 100 1.0 k 10 k 100 k 1.0 m 10 m f, frequency (hz) v cc = +15 v v ee = -15 v v cm = 0 v d v cm = 1.5 v t a = 25 c , output saturation voltage (v) sat r l , load resistance to ground (k w ) 0 1.0 2.0 3.0 4.0 , input common mode voltage range (v) v 600 500 400 300 200 100 0 v cc -0 v cc -0.5 v cc -1.0 v cc -1.5 v ee +1.5 v ee +1.0 v ee +0.5 v ee +0 50 30 20 10 40 10 8.0 6.0 4.0 2.0 0 160 140 120 100 80 60 40 20 v cc -1.0 v cc -3.0 v cc -5.0 v ee +5.0 v ee +3.0 v ee +1.0 cmr = 20log - + d v cm a dm v cm v o a dm d v o
mc33078, mc33079 http://onsemi.com 6 v o , output voltage (v ) pp r l = 2.0 k w f 10 hz d v o = 2/3 (v cc -v ee ) t a = 25 c r l = 10 k w c l = 0 pf f = 100 khz t a = 25 c figure 12. power supply rejection versus frequency figure 13. gain bandwidth product versus supply voltage figure 14. gain bandwidth product versus temperature figure 15. maximum output voltage versus supply voltage figure 16. output voltage versus frequency figure 17. open loop voltage gain versus supply voltage f, frequency (hz) p s r, p o wer s upply reje c ti o n (db) 100 1.0 k 10 k 100 k 1.0 m 10 m +psr -psr v cc = +15 v v ee = -15 v t a = 25 c v cc |v ee | , supply voltage (v) gwb, gain bandwidth product (mhz) 5.0 10 15 20 t a , ambient temperature ( c) g wb, g ain bandwidth pr o du c t (mhz) -55 -25 0 50 75 100 25 125 v cc = +15 v v ee = -15 v f = 100 khz r l = 10 k w c l = 0 pf v cc |v ee | , supply voltage (v) v , output voltage (vp) o 5.0 10 15 20 v o - v o + t a = 25 c r l = 10 k w r l = 10 k w r l = 2.0 k w r l = 2.0 k w f, frequency (hz) 10 100 1.0 k 10 k 100 k 1.0 m 10 m v cc = +15 v v cc = -15 v r l = 2.0 k w a v = +1.0 thd 1.0% t a = 25 c v cc |v ee | , supply voltage (v) vol a, open loop voltage gain (db) 5.0 10 15 20 140 120 100 80 60 40 20 0 30 20 10 0 20 15 10 5.0 0 20 15 10 5.0 0 -5.0 -10 -15 -20 35 30 25 20 15 10 5.0 0 110 100 90 80 +psr = 20log d v o /a dm d v cc a dm - + d v o v ee -psr = 20log d v o /a dm d v cc d v cc
mc33078, mc33079 http://onsemi.com 7 vol a, open loop voltage gain (db) figure 18. open loop voltage gain versus temperature figure 19. output impedance versus frequency figure 20. channel separation versus frequency figure 21. total harmonic distortion versus frequency figure 22. total harmonic distortion versus output voltage figure 23. slew rate versus supply voltage t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 v cc = +15 v v ee = -15 v r l = 2.0 k w f 10 hz d v o = -10 v to +10 v f, frequency (hz) | z|, output impedance () w 1.0 k 10 k 100 k 1.0 m 10 m o v cc = +15 v v ee = -15 v v o = 0 v t a = 25 c a v = 1000 a v = 100 a v = 10 a v = 1.0 f, frequency (hz) cs, channel separation (db) cs = 20 log d v oa d v om 10 100 1.0 k 100 k 10 k drive channel v cc = +15 v v ee = -15 v r l = 2.0 k w d v od = 20 v pp t a = 25 c mc33078 mc33079 f, frequency (hz) thd, total harmonic distortion (%) 10 100 1.0 k 10 k 100 k v cc = +15 v v ee = -15 v v o = 1.0 vrms t a = 25 c v o , output voltage (vrms) thd, total harmonic distortion (%) 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 v cc = +15 v v ee = -15 v f = 2.0 khz t a = 25 c a v = 1000 a v = 100 a v = 10 a v = 1.0 v cc |v ee | , supply voltage (v) falling 5.0 10 15 20 sr, slew rate (v/ s) m v in = 2/3 (v cc -v ee ) t a = 25 c rising 110 105 100 95 90 50 40 30 20 10 0 160 150 140 130 120 110 100 1.0 0.1 0.01 0.001 1.0 0.5 0.1 0.05 0.01 0.005 0.001 10 8.0 6.0 4.0 2.0 0 10 k w v om measurement channel - + 100 w 100 w v o 2.0 k w + - d v in v o 2.0 k w - + r a v in 2.0 k w v o + - 10 k w
mc33078, mc33079 http://onsemi.com 8 25 c -55 c 125 c v cc = +15 v v ee = -15 v d v in = 100 mv d v in v o c l - + v cc = +15 v v ee = -15 v v o = 0 v phase gain 125 c -55 c 25 c 25 c -55 c 125 c v in v o c l 2.0 k w - + gain phase v cc = +15 v v ee = -15 v r l = 2.0 k w t a = 25 c figure 24. slew rate versus temperature figure 25. voltage gain and phase versus frequency figure 26. open loop gain margin and phase margin versus load capacitance figure 27. overshoot versus output load capacitance figure 28. input referred noise voltage and current versus frequency figure 29. total input referred noise voltage versus source resistance sr, slew rate (v/s) m v cc = +15 v v ee = -15 v d v in = 20 v t a , ambient temperature ( c) falling rising -55 -25 0 25 50 75 100 125 f, frequency (hz) vol a, open loop voltage gain (db) 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m 0 45 90 135 180 , excess phase ( degrees ) f a, open loop gain margin (db) m 1 10 100 1000 0 10 20 30 40 50 60 f , phase margin (degrees) m 70 c l , output load capacitance (pf) c l , output load capacitance (pf) 10 100 1.0 k 10 k os, overshoot (%) 10 100 1.0 k 10 k 100 k 10 0.1 f, frequency (hz) e, input referred noise voltage () n nv/ hz v cc = +15 v v ee = -15 v t a = 25 c voltage current pa/ hz nv/ hz r s , source resistance ( w ) i , referred noise voltage ( n v cc = +15 v v ee = -15 v f = 1.0 khz t a = 25 c v n (total) = 10 100 1.0 k 10 k 100 k 1.0 m , input referred noise current ( ) n v) 10 8.0 6.0 4.0 2.0 120 100 80 60 40 20 0 14 12 10 8.0 6.0 4.0 2.0 0 100 80 60 40 20 0 100 80 50 30 20 10 8.0 5.0 3.0 2.0 1.0 1000 100 10 1.0 d v in v o 2.0 k w - + (i n r s ) 2 e n 2 4ktr s
mc33078, mc33079 http://onsemi.com 9 + - phase gain r 1 r 2 v o v cc = +15 v v ee = -15 v r t = r 1 +r 2 a v = +100 v o = 0 v t a = 25 c figure 30. phase margin and gain margin versus differential source resistance figure 31. inverting amplifier slew rate figure 32. noninverting amplifier slew rate figure 33. noninverting amplifier overshoot figure 34. low frequency noise voltage versus time , phase margin (degrees) a , gain margin (db) r t , differential source resistance ( w ) f m 10 100 1.0 k 10 k 100 k v cc = +15 v v ee = -15 v a v = -1.0 r l = 2.0 k w c l = 100 pf t a = 25 c v, output voltage (5.0 v/div) o t, time (2.0 m s/div) v cc = +15 v v ee = -15 v a v = +1.0 r l = 2.0 k w c l = 100 pf t a = 25 c v, output voltage (5.0 v/div) o t, time (2.0 m s/div) v cc = +15 v v ee = -15 v r l = 2.0 k w c l = 100 pf a v = +1.0 t a = 25 c v, output voltage (5.0 v/div) o t, time (200 m s/div) e, input noise voltage (100 nv/div) n t, time (1.0 sec/div) m 14 12 10 8.0 6.0 4.0 2.0 0 70 60 50 40 30 20 10 0 v cc = +15 v v ee = -15 v bw = 0.1 hz to 10 hz t a = 25 c
mc33078, mc33079 http://onsemi.com 10 figure 35. voltage noise test circuit (0.1 hz to 10 hz p p ) + - 0.1 m f 10 w 100 k w 2.0 k w 4.7 m f voltage gain = 50,000 scope 1 r in = 1.0 m w 1/2 mc33078 - + d.u.t. 100 k w 0.1 m f 2.2 m f 22 m f 24.3 k w 4.3 k w 110 k w note: all capacitors are nonpolarized.
mc33078, mc33079 http://onsemi.com 11 package dimensions pdip8 p suffix case 62605 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 so8 d suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
mc33078, mc33079 http://onsemi.com 12 package dimensions pdip14 p suffix case 64606 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 so14 d suffix case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc33078, mc33079 http://onsemi.com 13 notes
mc33078, mc33079 http://onsemi.com 14 notes
mc33078, mc33079 http://onsemi.com 15 notes
mc33078, mc33079 http://onsemi.com 16 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33078/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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